1. Field of the Invention
The present invention relates to a frequency synthesizer using a phase locked loop (will be termed "PLL" hereinafter).
2. Description of the Prior Art
FIG. 4 shows in block diagram a conventional PLL frequency synthesizer disclosed in the publication "Basics and Applications of PLL", written by Teruo Kadota, published by the Publication Department of the Electric College of Tokyo. In the figure, reference numeral 1 denotes a fixed-frequency oscillator, 2 is a frequency divider which divides a constant frequency generated by the oscillator 1 to produce a reference phase signal f.sub.r, and 3 is a phase comparator which compares an output phase signal f.sub.p of a programmable frequency divider 7 with the reference phase signal f.sub.r and uses the comparison output to control a charge pump 4. Indicated by 5 is a low-pass filter (will be termed "LPF" hereinafter) which smoothes the output of the charge pump 4, and 6 is a voltage-controlled variable-frequency oscillator (will be termed "VCO" hereinafter). The programmable frequency divider 7 divides the output frequency of the VCO 6 to produce the please signal f.sub.p.
Next, the conventional PLL frequency synthesizer arranged as described above will be explained. The fixed-frequency oscillator 1 has its output fed to the frequency divider 2, by which the oscillation frequency is divided. For the reference phase signal (reference frequency) f.sub.r of the frequency divider 2 and the frequency division factor N of the programmable frequency divider 7, the phase signal f.sub.o produced by the VCO 6 is related with the phase signal f.sub.p produced by the programmable frequency divider 7 as: f.sub.o =f.sub.p .times.N.
The phase comparator 3 controls the charge pump 4 to have a high output impedance when f.sub.p is equal to f.sub.r, to have a positive output voltage (supply voltage) when f.sub.p is higher than f.sub.r, or to have a ground voltage when f.sub.p is lower than f.sub.r. The LPF 5 is formed of a lag-lead filter, RC filter, active filter, or the like, and it smoothes the output of the charge pump 4. The smoothed output is fed to the VCO 6. The VCO 6 is designed to raise or lower its output frequency in response to an increase or decrease, respectively, of the input voltage (output voltage of LPF 5).
In the case of f.sub.r =f.sub.o /N, the charge pump 4 is in the high output impedance state, causing the LPF output to be unvaried, i.e., the input voltage to the VCO 6 is unvaried and it does not vary the output frequency, and the relation f.sub.r =f.sub.o /N is kept unchanged.
In the case of f.sub.r &gt;f.sub.o /N, the charge pump 4 produces a positive output voltage, which is applied to the LPF 5, causing it to supply an increased voltage to the VCO 6. Consequently, the output frequency of the VCO 6 rises, and the value of f.sub.o /N increases.
In the case of f.sub.r &lt;f.sub.o /N, the charge pump 4 produces a ground (zero) voltage, which is applied to the LPF 5, causing it to supply a decreased voltage to the VCO 6. Consequently, the output frequency of the VCO 6 falls, and the value of f.sub.o /N decreases.
Accordingly, a negative feedback loop is formed for the phase of the signal, and the operation settles when the output frequency of the VCO 6 becomes equal to N times the output frequency (reference frequency) of the frequency divider 2, i.e., f.sub.o =f.sub.p .times.N.
The phase comparator 3 operates continuously even in the steady state (the programmable frequency divider 7 has a constant division factor N and the VCO 6 has a constant output frequency). It is not possible to maintain a constant output voltage V.sub.f of the LPF, but instead the voltage V.sub.f continues to fall due to the power loss of the resistive components of the LPF 5, which is a .pi.-connection of resistors R1, R2 and R3 and capacitors C1 and C2 for example as shown in FIG. 5.
The VCO frequency also falls continuously, and the charge pump 4 operates to charge the LPF 5 by producing a positive voltage. As a result, the VCO 6 is always subjected to a pulse modulation at the reference frequency (this phenomenon will be termed "reference leak" hereinafter).
FIG. 6 shows the reference phase signal f.sub.r by (a) and the phase signal f.sub.p by (b) for the output phase signal f.sub.o of 500 MHz and frequency division factor N of 10000, as an example, in the steady state, resulting in a comparator output f.sub.pD Of 50 kHz, for example, as shown by (c), and a small reference leak R is created. The transition of the output phase signal f.sub.o following a change in the frequency division factor of the programmable frequency divider from N to M until the steady state is restored is generally called "step response".
As described above, the conventional PLL frequency synthesizer implements the phase comparison at the reference frequency, imposing a pulse modulation at the reference frequency on the VCO, 6. Therefore, it is necessary for the LPF 5 to have a low cutoff frequency. Moreover, the output step response following a change in the frequency division factor of the frequency divider until the settlement of steady state is deteriorated.